1. Field of the Invention
The invention relates to dynamic random access memories (DRAM), particularly with respect to the controller circuitry therefor.
2. Description of the Prior Art
DRAM technology is commonly utilized to implement the memory requirements for present day digital computers such as microprocessors. Generally, such memories are arranged in banks wherein a word location in a bank is accessed during a memory read or write cycle by row and column address signals. Thus, when addressing a memory location, the microprocessor provides a memory address that selects a memory bank as well as providing the row and column addresses for the desired location. In conventional DRAM design, the microprocessor provides the row address followed by the column address to a single address port serving the DRAM arrays. The row address is entered into the memory circuitry by a Row Address Strobe (RAS) issued by the microprocessor and similarly the column address is entered by a Column Address Strobe (CAS). Each bank of the memory has a RAS line input for strobing the row address signals therein. The bank selection portion of the memory address determines to which bank the RAS pulse is directed. DRAM arrays tend to be extensive having numerous memory banks requiring a large number of RAS lines.
The data stored in a DRAM cell requires periodic refreshing in order to maintain the data. A row of cells is refreshed by applying the row address to the memory address port while activating the RAS line. Traditionally, during a refresh cycle of a DRAM memory, corresponding rows in all of the banks are simultaneously refreshed by inputting the appropriate row address and simultaneously enabling all of the RAS lines. The rows of the banks are sequentially refreshed during sequentially performed refresh cycles by inputting sequential row addresses while simultaneously enabling the RAS lines for each row address. Thus, it is appreciated that for read/write memory access cycles, one of the plurality of RAS lines is enabled in order to access the appropriate bank. During memory refresh cycles, all of the RAS lines are simultaneously enabled.
In the configuration of the prior are invention described herein, the microprocessor provides the time multiplexed row and column addresses, the RAS and CAS pulses as well as a refresh request signal. In alternative microprocessor configurations, additional multiplexing and timing circuitry is utilized to provide some or all of these signals.
In order to perform the above-described functions, a DRAM controller is utilized. The controller includes decoding and bank selection logic that decodes the memory address into one of a plurality of bank selection lines which in turn provide the RAS signals, respectively. The bank selection lines are passed through refresh generating circuitry comprising logical OR functions responsive to the refresh request and RAS pulse usually derived from the microprocessor timing signals in order to individually energize the RAS lines during read/write memory access cycles and simultaneously energize the RAS lines during refresh cycles. In the prior art arrangement, a RAS signal bus containing one RAS line for each memory bank connects the DRAM controller to the DRAM bank array.
Thus, it is appreciated that circuitry for controlling the large amounts of dynamic RAM has traditionally involved the switching of a large number of RAS signals by the DRAM controller circuitry for the purpose of operating multiple banks of DRAM, one at a time. The RAS signals are mutually exclusive during read/write cycles enabling only one memory bank for any given memory read or write operation. However, for the periodically required refresh operation, all banks, or alternatively large groups of banks, are simultaneously enabled. Thus, DRAM circuits traditionally require that the RAS signals be driven individually one at a time, or that all be driven simultaneously. A considerable amount of circuitry and a large number of RAS signal conductors on the RAS signal bus connecting the controller to the memory array are required to perform these functions. Because of the large number of components required and the excess size of the electrical bus carrying the RAS signals that connects the memory array with the controller circuitry, a concomitant disadvantage of excess cost and physical space required for the circuit is also suffered. The cost of the individual circuits may also be excessive because of the requisite large number of electrical interconnections or I/0 pins from any integrated circuit designed to drive the DRAMs. The excessive number of circuits required in the prior art to perform the described functions also adversely impacts the speed of the circuit because the critical timing signals experience excessive propagation delays.